1. Field of the Invention
The present invention relates to a bus arbiter, and more particularly, to a bus arbiter for determining priorities for using a common bus using an interrupt signal or a privilege signal and a method thereof.
2. Description of Related Art
A data processing system including various functional blocks is typically implemented in a System On Chip (SOC) device. The SOC includes bus master devices, which share a common bus and/or memory. A bus arbiter controls access to the common bus so as to prevent, for example, bus master devices from simultaneously using the common bus.
FIG. 1 illustrates a data processing system 100 implemented as a SOC. The data processing system 100 includes a central processing unit (CPU) 102, which is a first bus master device, a second bus master IP1 104, a third bus master device IP2 106, a bus slave device IP3 108, and a bus arbiter 110. The CPU 102, the IP1 104, the IP2 106, and the IP3 108 share a system bus 120. Each of the IP1 104 and the IP2 106 can be a peripheral component interconnection (PCI) master controller, a direct memory access (DMA) controller, an Ethernet controller, or the like. The IP3 108 bus slave device can be, for example, a memory controller.
In the data processing system 100, the CPU 102, the IP1 104, and the IP2 106 send respective bus request signals REQ to the bus arbiter 110. The bus arbiter 110 determines a priority of bus use by selecting one from the CPU 102, the IP1 104, and the IP2 106 and sending a bus grant signal GNT to the selected device. The bus arbiter 110 determines a next master device to use the system bus 120, using an arbitrated priority list set in a conventional bus arbitration algorithm. An arbitrated priority list 210 of FIG. 2 can be stored in the bus arbitration algorithm.
In the arbitrated priority list 210, a certain bus occupancy rate (%) is set for each master device. The CPU 102 is assigned a%, the IP1 104 is assigned b%, and the IP2 106 is assigned c%. The a% for the CPU 102 is generally higher than the b% for the IP1 104 or the c% for IP2 106. Hence, in response to bus request signals REQ from the bus master devices 102, 104, and 106, the bus arbiter 110 controls the use of the system bus 120 so that a higher priority is given to the CPU 102 and a lower priority is given to the IP1 104 or the IP2 106.
In a Real Time Operation System (RTOS), which implements compression and decompression in real time, if the priorities of the bus mater devices 102, 104, and 106 are controlled in accordance with a fixed arbitrated priority sequence as shown in FIG. 2, the CPU 102 is always assigned a highest priority even when it has not requested use the system bus 120 to achieve fast processing. In other words, the RTOS cannot immediately respond to a bus request signal REQ from the IP1 104 or the IP2 106. Hence, the RTOS provides low bus use efficiency. Also, the RTOS cannot be expected to have high performance where the RTOS immediately responds to various operation patterns by dynamically switching the priority of use of the system bus 120 according to an adopted operating pattern.
Therefore, a need exists for a RTOS multi-processor system having improved system bus use efficiency.